Integrated semiconductor memories, particularly DRAMs (Dynamic Random Access Memory) have a multiplicity of memory cells that are arranged in a memory cell array and which are connected to word lines and bit lines. In the case of a DRAM, the memory cells respectively have a storage capacitor and a selection transistor. Other types of memory cells are also usually provided with a selection transistor. The selection transistors are usually in the form of MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) in which the gate electrodes are respectively sections of word lines. The selection transistors also comprise two source/drain regions, one of which is connected to the storage capacitor and the other source/drain region of which is electrically conductively connected to the bit line to which the memory cell is connected. The gate electrode is usually isolated by means of a gate oxide layer from a channel region which is arranged between the two source/drain regions in the substrate and in which an inversion channel flows at suitable electrode voltages.
To read a memory cell, the selection transistor is turned on and thereby makes the electrical connection between the trench capacitor and the bit line, as a result of which the potential of the bit line is altered according to the bias voltage on the transistor's capacitor electrode. Sense amplifiers compare the electrical potentials on two bit lines and spread the bit line potentials when reading and refreshing volatile memory cells. The sense amplifiers are therefore also called signal amplifiers or differential amplifiers, since they amplify the difference between electrical potentials.
Normally, each sense amplifier has two bit lines connected to it whose potentials are compared with one another by the sense amplifier. The two bit lines are called “True” and “Complement”, where “True” denotes that bit line to which the respective memory cell which is to be read is connected. The respective other (complementary) bit line is called “Complement”, since it is used only to provide a comparison potential, with respect to which the potential on the “True” bit line is altered after the charge previously stored in the memory cell which is to be read has been distributed over the entire “True” bit line. The sense amplifier identifies a resultant potential difference and then biases the bit lines with potentials whose potential difference is considerably greater than the initially identified potential difference and in any case has the same arithmetic sign. This allows data values which have been read to be written back or forwarded.
Depending on whether the two bit lines whose potential difference is measured and amplified by the sense amplifier are arranged on the same side or on opposite sides of the sense amplifier, reference is made to the “Folded bit line” concept or the “Open bit line” concept. In the case of the open bit line concept, the mutually complementary bit lines are routed away from the sense amplifier in opposite directions and on one and the other side of the sense amplifier, respectively, connect a plurality of memory rows to the sense amplifier. Running in a direction perpendicular to the two bit lines are word lines which can respectively be used to open a memory cell. A drawback of the open bit line concept is that when opening a particular memory cell the word line biased for it with the activation potential only runs past one of the two mutually complementary bit lines. In this case, the word line crosses the respective bit line in a conductor track plane below this bit line. Since the distance between the word line plane and the bit line plane is usually very short, capacitive couplings arise between the word line and the bit line, as a result of which the altered word line potential additionally influences the potential on the bit line to which the opened memory cell is connected. This capacitive coupling overlies the influence of the charges in the memory cell which has been read and thus has a noise effect which occurs only on one bit line in the bit line pair. In the worst case, this parasitic capacitive coupling can corrupt the reading result. This means that signals at a sufficient level are required which need to be ensured through significantly increased capacitance of the storage capacitor, for example.
By contrast, the folded bit line concept has the advantage that both mutually complementary bit lines are arranged on the same side of the sense amplifier and therefore each word line which is activated for the purpose of reading an arbitrary memory cell connected to one of the two bit lines is crossed by both lines together. This means that capacitive couplings always arise on both bit lines. Since the capacitive couplings from a word line activated for opening are of equal magnitude on both bit lines, the potential difference to be amplified between the two bit lines is not corrupted by capacitive noise influences in this case.
The folded bit line concept is also advantageous over the open bit line concept because the latter requires a second metallization plane in order to set up conductor track bridges for connecting the complementary bit lines routed to the sense amplifier on both sides to the switching elements of the sense amplifier. However, a drawback of the folded bit line concept is that each word line is crossed by both mutually complementary bit lines together which means that besides each crossing point, at which a memory cell is arranged, there is a further crossing point on the respective other bit line, at which no memory cells are present. Hence, along the course of the conductor track of both bit lines, a memory cell is provided only at the location of every second crossing. With sufficiently large memory cells having a substrate area of 8 F2 or larger (where F corresponds to the smallest lithographically produced feature size in the respective semiconductor circuit), it is admittedly possible to fill the entire substrate base area within the memory cell array with the memory cells and their reciprocal insulation without any unused substrate area remaining. However, as soon as memory cells are used which have a base area of less than 8 F2, for example 4 F2, unused substrate area with the size of the base area of a further memory cell or smaller remains at every second crossing, where no memory cell is provided. It is not possible to fit any additional memory cells at that point for reasons of circuitry, however, since each word line is permitted to short only one of the two mutually complementary bit lines with a capacitor from a memory cell connected thereto. This means that the folded bit line concept is disadvantageous in terms of the maximum packing density of memory cells per substrate base area as soon as memory cells with base areas of smaller than 8 F2 are provided.